1. Field of the Invention
The present invention relates to a semiconductor device with a package structure.
2. Description of Related Art
Recent years have witnessed an ever-increasing demand for miniaturization and an increase in the density of semiconductor devices that are mounted in electronic devices such as portable devices, as well as for higher frequency transmission signals. Accordingly, CSPs (Chip Size Packages) which are semiconductor devices packaged such that the outer dimensions thereof are substantially the same as the outer dimensions of the semiconductor chip have been attracting attention.
With a view to reducing fabrication costs and so forth, recent years have more particularly seen the active development of WCSP (Wafer-level Chip Size Package) technology (for example, Publication 1: Nikkei Microdevices, February 1999 Edition, pages 48 to 56, FIGS. 1 and 4), which are CSPs produced by means of completion as far as the external terminal formation step of a wafer not subjected to further processing, followed by the creation of individual packages by means of dicing and so forth.
Such WCSPs include those with a structure in which external terminals, and electrode pads on the semiconductor chip, are electrically connected via a wiring layer in which the external terminals are rearranged in desired positions. On account of being a re-distribution wiring layer or being patterned, the wiring layer is also called a ‘wiring pattern’.
WCSPs, which comprise this re-distribution wiring layer, afford the benefit of permitting increased freedom in the wiring design as a result of this re-distribution wiring layer.
On the other hand, for the purpose of implementing high density mounting, recent years have seen the application of stacked package-type MCPs (Multi Chip Packages) in which a plurality of chips are arranged in planar fashion or stacked in the thickness direction of the semiconductor chips within a single package (for example, Publication 2: Nikkei Microdevices, February 2000 Edition, pages 50 to 52, FIG. 1).
Furthermore, as a structure that raises the mount density still further, package stacked-type MCPs in which a plurality of packages are stacked in the thickness direction of the semiconductor chips are currently being proposed (for example, Publication 3: Amkor Technology etCSP™, See Internet URL: http://www.amkor.com/Products/all_products/etcsp.cfm).
However, because the WCSPs that comprise the re-distribution wiring layer described above are packages whose outer dimensions are substantially the same as the outer dimensions of the semiconductor chip as described earlier, there are limits on the number of external terminals that can be arranged on the mount face.
Stated in more detail, because current WCSPs have a fan-in structure, that is, a structure in which the external terminals are arranged above the semiconductor chip, the maximum number of external terminals that can be arranged is as many as about 160 (pins), and the minimum interval (pitch) between the external terminals is then about 0.5 mm.
In order to meet the demand for a greater number of pins in accordance with the higher integration of recent years, it is necessary to narrow the minimum interval between external terminals to about 0.4 mm, for example.
However, although setting the interval between external terminals at about 0.4 mm is technically feasible, such a practice is undesirable due to the requirement for a high density mounting technology when mounting the WCSP on the mount substrate.
Furthermore, in the case of a multiple pin class of about 300 pins, however narrow the external terminal interval may be, it is sometimes difficult to arrange all the pins on the mount substrate.
Therefore, BGAs (Ball Grid Arrays) and LGAs (Land Grid Arrays) that adopt a wire bonding (sometimes referred to simply as ‘WB’ hereinafter) method have been proposed, these being packages in which a semiconductor chip is mounted on a wiring substrate and having a structure that allows external terminals to be arranged over the whole of the reverse side of the wiring substrate.
However, since the inductance of the WB parts is high in the case of such structures in which the wire bonding (sometimes referred to simply as ‘WB’ hereinafter) method is normally adopted, impedance matching with the circuit in the semiconductor chip is problematic. Furthermore, because a wiring substrate that comprises bonding pads, and so forth, is required, not only does this lead to a thick package, fabrication costs are also increased.
Meanwhile, the flip chip method has been proposed as a wireless bonding method. However, because the interval between pads (electrode pads) on the semiconductor chip is then equal to or less than 0.1 mm, an expensive build-up substrate is required, and the flip bonding processing takes a long time. Hence such a method is not suited to mass production.
Further, also with the above-described stacked package-type MCPs, in the case of a structure that adopts the WB method, problems are produced which include increased inductance and an increase in the package outer dimensions and package thickness, and so forth, which are caused by WB, as described earlier.
Moreover, even with the above-described package stacked-type MCPs, in the case of a structure that adopts the WB method, not only are there problems that include increased inductance and an increase in the package outer dimensions and package thickness, and so forth, which are caused by WB, as described earlier, an increase in the number of pins of the MCP is also unsuitable because a fan-in structure cannot be achieved.
Accordingly, it is an object of the present invention to provide a semiconductor device whereby, on the basis of a WCSP structure for which a still wider range of application will be sought in the future, an increase in the number of pins through an enlargement of the mount face can be implemented, greater miniaturization than that known conventionally (miniaturization of the package size and thinner films) is achieved and a package stacked-type MCP and the like can be designed.